1. Field of the Invention
The present invention relates to a display device having a light-emitting element, a liquid crystal element and the like, and a driving method thereof.
2. Description of the Related Art
With respect to a flat panel display device which is widely used for a display portion of a portable information terminal as well as medium and large sized devices in recent years, the number of pixels has increased as the display device has been highly defined. Therefore, it is necessary that video signals can be written into each pixel taking enough time by a line sequential driving method in which data is simultaneously written (input) to each row of active matrix pixels each of which can hold image data, even if the number of pixels is large.
A gray-scale system of a display device having active matrix pixels is broadly categorized into an analog gray-scale system and a digital gray-scale system. Between the two, the digital gray-scale system includes a time division gray-scale system, an area gray-scale system, and a combined system of the two systems. In any of the digital gray-scale systems, each pixel or sub pixel is driven with a binary value of an on state or an off state. Therefore, the digital gray-scale system has an advantage in that image quality is prevented from being deteriorated by variation of Vth of TFTs in comparison with the analog gray-scale system. Note that Japanese Patent Laid-Open No. 2001-5426 also discloses a gray-scale display using the digital time division system.
FIG. 5 shows a configuration example of a digital gray-scale display device for inputting data having a binary values into active matrix pixels by a line sequential system. A pixel portion has M rows and N columns of pixels (M and N are natural numbers respectively). Around a pixel portion 501, a source line driver circuit 502 having a shift register 504, a first latch circuit 505, a second latch circuit 506, a level shifter 507 and a buffer 508, and a gate line driver circuit 503 having a shift register 509, a level shifter 510 and a buffer 511 are arranged.
The shift register 509 outputs selective pulses sequentially from a first stage in accordance with clock signals (GCK) and start pulses (GSP). After that, the level shifter 510 converts the amplitude of the selection pulses, and the buffer 511 selects gate lines sequentially from a first row to m-th row and then to M-th row (2≦m≦M, m is a natural number).
At a row of which a gate line is selected, the shift register 504 outputs sampling pulses sequentially from a first stage in accordance with clock signals (SCK) and start pulses (SSP). The first latch circuit 505 samples video signals (Video) at the timing when sampling pulses are input, and the video signals sampled on each stage are held in the first latch circuit 505.
As a latch pulse (LAT) is input after video signals of one row are completely sampled, the video signals held in the first latch circuit 505 are transferred to the second latch circuit 506 all at once so that all source lines are charged and discharged all at once. Accordingly, when a latch pulse (LAT) is input after video signals of the m-th row are completely sampled, the video signals held in the first latch circuit 505 are transferred to the second latch circuit 506 all at once so that all source lines are charged and discharged all at once through the level shifter 507 and the buffer 508.
The abovementioned operations are repeated from the first row to the last row (here, the M-th row) so that writing into all pixels is completed. In addition, similar operations are repeated to display video.
In the case of the analog gray-scale system, if data is input to a source line at least once in each frame, gray-scale display is enabled.
On the other hand, in the case where the digital gray-scale system is used by which each pixel is driven with a binary value of an on state and an off state, such as the time gray-scale system, the area gray-scale system, or the combination of the time and area gray-scale systems, data is required to be input to a source line a plurality of times in each frame in order to perform gray-scale display. In a display device, a plurality of TFTs provided in a pixel portion and parasitic capacitance is load capacitance to a source line connected to a buffer circuit. In the case of a digital gray-scale system, when data input into a source line changes from a low potential ((m−1)-th row) to a high potential (m-th row), an external positive power source charges the load capacitance until it reaches from the low potential ((m−1)-th row) to the high potential (m-th row) through p-channel TFTs of the buffer. On the contrary, when data input into a source line changes from a high potential ((m−1)-th row) to a low potential (m-th row), an external negative power source discharges the load capacitance until it reaches from the high potential to the low potential through n-channel TFTs of the buffer. The electric power is consumed when an electric potential of a source line changes; therefore, if an output often changes, more electric power of the external power source is consumed. Therefore, in the case of the digital gray-scale system, power consumption of the external power source increases in order to display an image such as a natural picture which requires a number of gray scales or a specific pattern in which logic is frequently inverted, because a voltage is changed many times upon data input into a source line.
Therefore, in the case of the digital gray-scale system, power consumption required for inputting data into a source line is a big problem for a small sized display device of a portable terminal which requires low power consumption. Further, with respect to display devises such as a television, it is difficult to prevent an increase of parasitic capacitance of a source line in accordance with the increase in size of the display devices. Therefore, it requires lower power consumption similarly to a small-sized display device.